A semiconductor-integrated-circuit SRAM cell is a memory cell, in the form of electrical circuitry integrated in a semiconductor body, that retains its binary digital memory storage state (i.e., a 0 or a 1: a low or a high) for as long a time as dc electrical power is applied to the cell or until it is written again with a different binary digital signal (i.e., a 1 or a 0, respectively). In one design, such a cell is formed by a pair of cross-coupled transistors, each of the transistors being connected in series with a separate load device. Each of these load devices can simply be a resistor such as provided by suitably connected transistor (diode). In another design, such a cell is formed by electrical circuitry comprising two pairs of cross-coupled transistors connected in series with each other--one pair comprising a pair of cross-coupled n-channel MOS (Metal Oxide Semiconductor) transistors, and the other pair comprising a pair of cross-coupled p-channel MOS transistors. In any event, the semiconductor body in which a cross-point memory array is integrated is typically silicon, but it is known that similar arrays can be constructed in other semiconductor bodies such as compound Group III-V semiconductors like GaAs (gallium arsenide).
An array of SRAM cells can take the form of one or more columns of SRAM cells in which each such cell is located at (and is electrically connected at) an intersection of a single (electrically conductive) row line with a single (electrically conductive) column line B. Each such row line carries an electrical signal, whereby (during any read-write cycle) it can select which desired row of the cells shall be written or read. The determination of whether a cell, which is thus selected by the row line, shall be written versus shall be read during a given read-write cycle is made by external circuitry connected to the (electrically conductive) column line B.
External electrical access either for reading or for writing desired cells--for example, simultaneous access to as many as all the cells located on a selected row of cells--is desired in such arrays. Access transistors intervene between the column lines and the cells--one or more such access transistors per cell--to control the flow of the data (0's and 1's) between the column lines and external sense (detector) circuitry and external data-source circuitry, and thus to control the selection by the row lines of the cells that are to be written or are to be read
More specifically, in order to facilitate the writing (at various moments of time) of either a 0 and a 1 state into a cell, at least two access transistors per cell is desirable, whereby each column of cells requires at least two column lines (e.g.., a pair of complementary column bit lines typically labeled B and B). At any moment of time, one of these column lines carries the opposite digital signal (if any) from the other. In addition, each cell requires electrical power, such as is provided by a column VDD line and a column VSS line, where VDD is typically in the approximate range of 1 volt to 5 volt, and where VSS is typically ground (0 volt).
In some practical applications of SRAM cell arrays, a capability of reading one cell located on a given column and simultaneously (i.e., during a single read-write cycle) writing another cell located on the same given column is desirable: this capability allows a desirably faster overall performance. This capability will be referred to as a "simultaneous read-write" capability.
To this end, a paper by H. Kadota et al published in IEEE Journal of Solid-State Circuits, Vol. SC-17, pp. 892-897 (1982) and entitled "A New Register-File Structure for the High-Speed Microprocessor" teaches circuitry for accessing an SRAM cross-point-memory-cell array. Also, a paper by Kevin J. O'Connor published in IEEE Journal of Solid-State Circuits, Vol. SC-22, pp. 712-719 (1987) and entitled "The Twin-Port Memory Cell" teaches [at FIG. 2(b)] circuitry for accessing such an array. The circuitry taught in those papers involved arrays of "dual-port" SRAM cells--i.e., SRAM cells in which electrical access to (and hence selection of) each cell is provided by four column lines per column of cells (a pair of column lines located on either side of the cell) while each column line of a given pair carried the opposite binary digital signal from the other. In addition, access to (and hence selection of) each cell located on a given row was controlled by a pair of row lines (one such pair for each such row of cells): one of the pair controlled the reading while the other of the pair independently controlled the writing of the cells located on the row. Detection of the 0 vs. 1 memory state of a selected cell was accomplished by means of a voltage sensing device, such as an amplifier and flip-flop circuitry. Such dual-port cells, when located in an array having more than a single row, thus achieved the above-mentioned simultaneous read-write capability. In addition, such dual port cells (as a result of being dual port, i.e., having two pairs of column bit lines associated with each cell) enjoyed the advantage of not requiring boosted (higher-applied-voltage) row lines.
The circuitry taught in the above-described prior art, however, required a total of four column lines plus two column power lines for each column of cells, in addition to two row lines, whereby an undesirable amount of added precious semiconductor area was needed to accommodate the total of six column lines plus the two row lines. It would therefore be desirable to an SRAM cross-point-memory-cell array having fewer than six column lines per column of cells while retaining the above-mentioned read-write capability.